Physical Bottlenecks in AI Clusters
Examines physical constraints across high-speed interconnect fabrics, advanced packaging, and global chip manufacturing supply chains.
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Oct 27, 2026
Oct 24, 2026
Oct 23, 2026
- SemiAnalysis ASML’s unannounced hybrid bonder would bring its front-end precision into a market led by Besi and other placement specialists. The case rests on 2025 patent filings, with deployment “several years out.” Dies would stay on conveyor carriers through preparation and …
- Howie Production yield and supplier integration are the critical execution questions for ASML’s conveyor design. Bonding requires six-axis alignment and particle-free surfaces; a single contaminant can wedge open a wider area. Howie questions how moving …
- China’s logic-folding roadmap creates another source of demand for hybrid-bonding tools. Howie cites a Huawei phone and its partitioned design, saying it can reach 2.7 GHz, plus roadmaps targeting fully hybrid-bonded data-center …
- The clearest evidence of diverging technology paths is already in chip design. Howie contrasts AMD’s cache stacking with Huawei’s partitioning of components inside a core across layers. Sherry sees domestic localization …
- Sherry Zhang Larger High-NA masks would restore full reticle area and support higher ASML tool prices. Around 2030, 6-by-12-inch masks are intended to overcome the roughly 400 mm² half-field limit versus 850 mm² today, requiring changes across …
Oct 22, 2026
- Dwarkesh Podcast Available equipment may support about 2X leading-edge wafer output, not 10X; 2030 supply depends on broader capacity growth. An opening, unidentified Intel speaker says AI demand is “easily 40–50% above our maximum capacity.” Dwarkesh notes that ASML makes fewer …
- Ranade argues Intel is within a few percent of TSMC technologically; scale and execution remain important gaps. He says that within a few percent on performance, power, or density, “you’re splitting hairs,” and that on-time delivery and yields …
- High-NA EUV is an architecture-dependent choice, not simply a tool race. Chris Auth explains that Intel’s backside power relaxes some front-side pitch requirements, making High-NA useful for Intel; TSMC’s tighter …
- Long-range 3D structures are a possibility, with thermals a limiter—not a firm 2045 forecast. Auth discusses transistors floating within interconnect and asks what more extensive 3D structures might enable over a 10- or 20-year …
- Hybrid bonding has room to scale, but its densest future uses remain prospective. Tyler Osborn gives the progression from 130–150 µm first-level interconnect pitch 15 years ago, to 25 µm in Foveros high-volume …
- Rising costs invite radical questions in a risk-averse industry. Ranade says fab costs have been doubling every 4–5 years and puts a High-NA scanner plus associated equipment at around $400 million. He …
Oct 16, 2026
Oct 15, 2026
Oct 10, 2026
- Pat Gelsinger AI has compressed logic design faster than it has compressed the path to deployed silicon, shifting value toward fabrication, packaging, memory, power, cooling, and rack-scale integration. Gelsinger’s diagnosis is “it’s no longer a chip, it’s a rack”: a three-month design can face nine months for silicon and another three for …
- The a16z Show The field of roughly 100 AI processor vendors is a transitional boom, not a durable market structure. Raghu framed the number as historically unprecedented; Guido predicts consolidation because workloads will evolve beyond today’s …
- Optics should displace copper for scale-up I/O around 2028–2029, though not inside the core compute-memory complex. Gelsinger argues that it is already “more expensive to make copper work at 5 meters than to make optics work at 100 meters”; the remaining …
Oct 7, 2026
Oct 3, 2026
- Vikram Sekar Training remains a coherent-cluster problem, while inference is becoming a “Wild West” of architectures. Moving beyond 72-GPU, roughly 200 kW Blackwell racks toward 144 GPUs implies more than 400 kW plus harder cooling and networking; spreading …
- The near-term scaling trade is increasingly optical because copper is reaching a physical limit. Copper works inside a rack at 200 gigabits per second, but cannot span roughly 10 meters across eight racks; at 400 gigabits, Vikram says it …
Oct 2, 2026
- Walter Goodwin Goodwin sees much of today’s AI-chip variety as architecturally similar beneath the branding. NVIDIA and AMD GPUs, hyperscaler ASICs, and TPUs commonly rely on HBM, tensor cores, and TSMC advanced packaging. Fractile’s differentiation …
- The company’s roughly 150-person, vertically integrated team is designed to shorten the feedback loop between workload research, architecture, physical design, packaging, and foundry interaction. Goodwin argues that a durable three-to-six-month lead can decide deployments: “If you find a way to structurally secure a three- to …
- Goodwin expects frontier labs to keep buying from multiple hardware suppliers even as they develop proprietary silicon. In-house chips provide bargaining power, supply diversity, and control, but exclusive dependence is dangerous: a rival’s fivefold …
Oct 1, 2026
- Annie Lamont AI’s investable bottlenecks now center on power, memory, cooling, and data transfer. Adam identifies these constraints; Stephen says physical components are harder to improve overnight. Micron, SK hynix, and Samsung account …
- Moore’s Law is reaching a physical plateau after decades of transistor scaling. Stephen puts the transistor’s dimension near 1 nanometer—roughly 100,000 times smaller than a human hair—forcing hardware solutions to …
Sep 30, 2026
- Yannick De Koninck AI’s next bottleneck is the fabric connecting GPUs, not merely the GPUs themselves. Models no longer fit on a single GPU, while agentic systems add latency-sensitive calls across servers; Yannick De Koninck says this demands …
- Sourcery The investable scarcity sits across the manufacturing chain, not in photonic science alone. TSMC, GlobalFoundries, and Tower have invested in silicon-photonics wafers, but “if you deliver a wafer to NVIDIA, that’s not what they …
- Herwig Van Hove NVIDIA’s escalation turned a long-anticipated transition into an immediate capacity problem. Van Hove dates the demand shock to ChatGPT’s viral release in November ’22, followed by louder signaling from NVIDIA in ’24 and ’25 and …
- Sourcery Themaa is using an acquired European foundry to compress a new-facility build into a 2027 production target and 2028 full ramp. Located 20 kilometers from imec, the facility combines ready infrastructure with photonics and industrial talent. Customers are requesting …
- Europe’s photonics opportunity is credible, but execution culture is the test. Belgium has unusually deep research density—Van Hove says the University of Ghent produced 35% of 4,000 global peer-reviewed white papers on …
Sep 29, 2026
Sep 25, 2026
- P Equity Research Today’s compute shortage is really a compound constraint spanning chips, memory, packaging, power, and construction. CLSA estimated a 73% gap between ASIC/GPU demand and supply through 2030, B200/B300 rental rates reportedly rose from roughly $5 to $7-8 per …
- The less obvious supply constraints sit in ABF substrates, printed circuit boards, and possibly indium phosphide, while networking broadens the trade. ABF capacity may remain constrained beyond 2028, while networking capex could compound around 64% annually for five years. These constraints …
- Copper and optics will coexist longer than optical bulls may expect. Near-package optics could scale in 2027 and co-packaged optics in 2028-29, but heat, yield, and cost may delay CPO dominance until after …
Sep 23, 2026
Sep 21, 2026
- Bubble boi Bubble boi’s investable thesis is that AI’s binding constraints are migrating from transistor shrinkage into packaging, interconnect, and memory. Moore’s Law once delivered roughly twice the transistor density every two years; now tens or hundreds of billions of dollars may buy only …
- NVIDIA’s roadmap depends increasingly on suppliers and technologies it does not control. H100 used one large die, B200 moved to two, Reuben used two by default, and the Ultra design was intended to reach four—yet repeated …
- AI hardware must now be designed as a rack-scale system, not an isolated accelerator. NVIDIA’s NVL72 connects 72 packages and uses roughly four NVLink switches, while the TPU team reportedly stretches its scale-up domain to …