What will computer chips look like in 2045?

Summary

• Available equipment may support about 2X leading-edge wafer output, not 10X; 2030 supply depends on broader capacity growth. An opening, unidentified Intel speaker says AI demand is “easily 40–50% above our maximum capacity.” Dwarkesh notes that ASML makes fewer than 100 EUV machines a year and describes limited plans to increase that materially by decade’s end. Asked whether the world has enough tools to 10X leading-edge wafers, Pushkar Ranade answers, “Not 10X, but probably 2X, yes.” Dwarkesh’s later timeline summary puts tool orders placed now into ’28 and a new fab shell near the end of the decade; Ranade does not explicitly confirm that summary. The claim that AI’s decade of 3X annual compute growth “just can’t continue” is Dwarkesh’s framing.
• AI labs securing fab-scale capacity is a possibility raised by Dwarkesh, not a commitment from Ranade. Dwarkesh’s calculation is that a couple billion dollars of Intel CapEx could support the logic behind roughly $100 billion a year in AI-model revenue; he also notes that memory and other parts of the stack matter. He speculates that AI labs might buy or guarantee supply. Ranade says some model companies could consume an entire fab’s worth of silicon and have the capital to fund it, but the “early signs” of this shift are Dwarkesh’s characterization. Ranade’s closing response to the suggestion that Intel buy more tools: “Had we known what we know today, we would have invested more like a year ago. Knowing what we know now, I think we’ll be investing more.”
• Ranade argues Intel is within a few percent of TSMC technologically; scale and execution remain important gaps. He says that within a few percent on performance, power, or density, “you’re splitting hairs,” and that on-time delivery and yields supporting rapid ramps matter more. He disputes Dwarkesh’s cited SemiAnalysis benchmarking of 14A against N2. Dwarkesh cites TSMC shipping upwards of 3X Intel’s leading-edge wafers and spending about $50 billion on CapEx versus Intel’s roughly $20 billion. Ranade says about 80% of a fab’s cost structure is fixed, making utilization and yield improvements especially valuable; he notes there are now only three foundries at the advanced node, down from about 20 forty years ago.
• High-NA EUV is an architecture-dependent choice, not simply a tool race. Chris Auth explains that Intel’s backside power relaxes some front-side pitch requirements, making High-NA useful for Intel; TSMC’s tighter pitches without backside power require double-patterning EUV. “For them, it’s not very helpful. For us, it is very helpful.” Intel’s 10nm experience—originally targeted for 2016, with manufacturing starting in 2018—taught it to limit per-node innovation and use phase-gate maturity metrics. 14A is planned to have a high-quality PDK from the outset, after 18A “started out not having a PDK.”
• Intel’s memory exits look costly amid today’s shortage, though Ranade says the demand was unforeseeable; Terafab is another response to demand. Ranade says the supply crunch is larger for memory than compute, while noting that nobody could have seen the scale of demand when Intel exited DRAM and flash. He says Intel is working with Elon to help accelerate his fab project. Dwarkesh points out that tool shortages could mean a new fab secures supply without increasing net global silicon; Ranade adds that power, water, and consumables are also required, and says those inputs can be scaled more readily than tools.
• Long-range 3D structures are a possibility, with thermals a limiter—not a firm 2045 forecast. Auth discusses transistors floating within interconnect and asks what more extensive 3D structures might enable over a 10- or 20-year horizon. He calls heat dissipation a limiter for 3D devices, while saying the system-level analysis and simulation tools are still in their infancy. Separately, Dwarkesh cautions that technology roadmaps often have only about four years of visibility.
• Hybrid bonding has room to scale, but its densest future uses remain prospective. Tyler Osborn gives the progression from 130–150 µm first-level interconnect pitch 15 years ago, to 25 µm in Foveros high-volume manufacturing today and sub-10 µm in development. He cites a paper presented at this year’s IEEE ECTC with reliability data on a 0.45 µm-pitch device. He says finer bonding could eventually connect lower interconnect layers across chips and reduce power; the potential to approach on-die interconnect is a future possibility, not a current production capability.
• Rising costs invite radical questions in a risk-averse industry. Ranade says fab costs have been doubling every 4–5 years and puts a High-NA scanner plus associated equipment at around $400 million. He questions whether patterning costs can keep rising at that rate, and asks, “Do you really need a clean room today?” He says no incumbent would willingly test a fab with people eating hamburgers and smoking cigars inside. Kevin Fischer’s operating principle: “If you want to wait for a complete data set, you’ve waited too long.”

Deep dive

1. Bringing up 14A means fine-tuning 2,000 steps — and learning from 10nm

• Chris Auth describes 14A as more than three years into development and close to finalizing the process and tool sets. The factory has roughly 2,000 steps, each needing intricate tuning so the process can run thousands of wafers a week repeatably. Defects are found through inline metrology and end-of-line electrical testing; TEM cross-sections can locate a defect between layers and help identify which section of the flow produced it.
• Auth’s account of 10nm: Intel set aggressive “hyperscaling” targets and developed ideas to reach them without new tools because EUV was not ready. The node eventually achieved world-class yield, performance, and cost, but took longer than intended: its original target was 2016, and manufacturing did not begin until 2018. A news clip in the transcript has Intel’s stock down more than 15% and TSMC up 13%. TSMC used EUV in volume from 2019; Intel’s first EUV process reached products in 2023, leaving TSMC with about four more years of experience with the machines.
• The institutional response includes phase-gate maturity metrics for yield, defects, and performance, used to decide whether technology can move from pathfinding into development. Auth’s principle is to limit innovation per node so the process can meet the customer’s schedule.

2. High-NA makes sense for Intel and not TSMC — because of backside power

• Dwarkesh explains the tool economics: High-NA widens numerical aperture from 0.33 to 0.55 and can print features about 1.7 times smaller in a single pass. Standard EUV machines cost around $200 million, while High-NA machines cost about twice as much. The value depends on how many patterning passes the tool can eliminate; extra passes take time and introduce more opportunities for defects.
• Auth says Intel and TSMC can reach different conclusions from the same tool because their technology architectures differ. Backside power alleviates some front-side pitch requirements, allowing Intel to print some patterns directly with High-NA. TSMC’s tighter pitches without backside power require double-patterning EUV, so the tool is less useful to them. At 14A, High-NA is an option in the PDK and will be discussed with customers individually.
• On Intel’s foundry learning curve, the transcript says decades as an IDM meant it had not had a formal PDK-type process; 18A “started out not having a PDK.” Customer feedback has informed the process, and 14A is planned to have high-quality PDKs from the outset, with maturity levels such as 0.5, 0.9, and 1.0.

3. From “try to not change anything” to the sledgehammer era

• Auth contrasts the ’80s and ’90s, when Dennard scaling and lithography drove predictable shrinking, with the “golden age of innovation” that began when scaling alone was no longer enough. Strained silicon, high-k metal gate, FinFETs, gate-all-around, and backside power expanded the process playbook. He estimates the number of materials used has increased about 10X since the ’90s: “Before, it was ‘try to not change anything.’ Now it’s ‘take the sledgehammer and start tearing the thing up.’”
• Gate-all-around took a long time to reach production partly because other options could deliver performance first. Auth says, “you don’t want to tackle something before you have to”: Intel used strained silicon, high-k metal gate, and FinFETs before taking on gate-all-around. New materials, tools, gases, and heating equipment can require invention by suppliers, and development involves iterating on structures that fail.
• In a discussion of long-range possibilities, Auth calls gate-all-around “somewhat inevitable,” while describing stripping the substrate and placing wires on the backside as “a little bit out there.” He considers whether future chips could combine transistors and interconnect in more extensive 3D structures, looking at a 10- or 20-year horizon. Dwarkesh adds that technology roadmaps often have only about four years of visibility.
• Auth describes three limits on compute: switching frequency, power per switch, and heat dissipation. For 3D devices, system-level thermal analysis and simulation are still in their infancy. Thermals are a limiter, he says, but “these are problems that we can go solve.”

4. Inside the Hot Topics meeting: incomplete data, epi tumors, and HotBox 1

• Kevin Fischer, who helps decide how engineering resources are allocated to 18A problems, says, “You will never have a complete data set. If you want to wait for a complete data set, you’ve waited too long.” His job is to decide how much risk to take: “Do we go now? Do we start risking production?” He says many engineers do not see how the work affects Intel’s bottom line or customers.
• The example is epi nodules: abnormal epitaxy growth “like a tumor” that grows quickly and can cause one epi to short to the wrong epi, leaving transistors not working. Teams work in parallel on potential fixes, including a special clean to remove nodules and ways to eliminate their source; the first fix that seems promising is not always the one that works.
• Experiment lots can use a tiered system of “hot boxes.” The highest priority, HotBox 1, gets priority at every tool and races through the factory, but Fischer says it is a drag on factory efficiency. His analogy is reserving a carpool lane for a single experiment.

5. In the research lab: ruthenium, cobalt’s round trip, and CFET’s integration challenges

• Jack Kavalieros explains why Intel is exploring ruthenium for very fine-pitch interconnects. Copper typically needs a liner to help deposit it and connect it to underlying copper; the liner can occupy a significant part of the conduction path. Ruthenium can be etched without that liner, and Kavalieros says there is a crossover at roughly 20-nanometer pitch where ruthenium can have better conductivity than copper.
• The cobalt example shows how materials choices can change. Cobalt was the leading option when Intel made its decision, but later solutions brought copper back into contention. Kavalieros says every technology is evaluated against alternatives as the manufacturing time horizon approaches.
• CFET research uses short-loop vehicles to get faster results than the month or longer required for a full manufacturing flow. Teams can begin with components such as diodes and capacitors, then combine them into transistors. A simplified CFET might use one wire for the NMOS and one for the PMOS, rather than four ribbons stacked on four ribbons. The difficult parts include vertical interconnection, high-aspect-ratio etches, and filling tiny spaces without air gaps.
• Dwarkesh asks why a lab version does not mean CFET is ready for a phone, and raises a ten-year timescale in his question. The answer is not a firm production timeline: the lab version is simplified and may not outperform side-by-side nanoribbons. The technology must evolve through many steps, including the right metals and dielectrics. Materials can fail because contacts do not adhere or because later processing interacts with a film that is not hermetically sealed.

6. Hybrid bonding is dissolving the boundary between packaging and chip

• Tyler Osborn contrasts wafer-to-wafer bonding, which is popular in CMOS image sensors, with chip-to-wafer bonding. Wafer-to-wafer requires closely matching dies and sort maps; random differences between good and bad dies can reduce yield. Chip-to-wafer lets manufacturers test and select known-good dies before bonding them to known-good positions. Osborn expects both approaches to be used and says chip-to-wafer makes sense for logic-to-logic.
• The pitch progression is 130–150 µm for first-level interconnect 15 years ago, 25 µm in Foveros high-volume manufacturing today, and sub-10 µm in development. Osborn cites reliability data on a 0.45 µm-pitch hybrid-bonded device in a paper at this year’s IEEE ECTC; this is not presented as current high-volume production. He sees room for further scaling.
• Osborn says that if packaging reaches around 0.5 µm or below, it could become possible to connect lower interconnect layers across chips, potentially reducing total IR drop. For non-AI uses, including client devices, he points to interconnect density and lower power per bit, which could mean less heat for the same electrical performance.

7. The supply ceiling: 2X is possible, 10X is not

• An unidentified Intel speaker at the beginning of the transcript says AI demand is “easily 40–50% above our maximum capacity, which I’ve never seen before.” Later, Dwarkesh notes ASML’s EUV output is fewer than 100 machines a year and says it is not expected to rise significantly by the end of the decade. Ranade calls EUV a limiter, but says shortages extend across equipment: once a process such as 18A is locked to a particular tool, Intel cannot simply substitute another supplier’s tool.
• Asked whether the world has enough tools to 10X leading-edge wafer production, Ranade answers, “Not 10X, but probably 2X, yes.” Dwarkesh says that means the AI industry’s 3X annual compute growth “just can’t continue” without the supply chain, including sub-suppliers, producing more; that is Dwarkesh’s conclusion.
• Dwarkesh later offers a timeline summary: marginal output might rise within about 12 months, but 2030 production may not be much higher than forecasts; an 18-month tool lead time puts new orders into ’28, with a new shell pushing out toward the end of the decade. The transcript does not include Ranade explicitly confirming that summary. For 14A, Ranade says Intel tries to preserve fungibility between nodes; perhaps 80% of the 18A tool set can be reused.

8. A couple billion of CapEx and $100B of AI revenue — a capacity-buying scenario

• Dwarkesh’s calculation is that a couple billion dollars of Intel CapEx could support the logic behind roughly $100 billion a year of AI-model revenue, while noting that memory and other players in the stack also matter. He speculates that AI labs might buy everything or guarantee future supply. Ranade says some model companies have enough demand to consume an entire fab’s worth of silicon and the capital to fund it; the transcript’s “early signs” of this shift are Dwarkesh’s framing, not Ranade’s.
• On Terafab, Ranade says Elon saw that his businesses would need a lot of silicon and Intel thought it could help accelerate the process of bringing up a fab. Dwarkesh points out that a tool bottleneck could mean a new fab secures guaranteed supply without increasing net global silicon. Ranade adds that a fab also needs power, water, and consumables, and says those inputs can be scaled more readily than tools.
• After Dwarkesh suggests Intel should commit to more tools, as Nvidia reportedly has for memory and other components, Ranade responds: “Had we known what we know today, we would have invested more like a year ago. Knowing what we know now, I think we’ll be investing more.”

9. Catching TSMC is about scale, not just transistor density — and memory is also constrained

• Ranade says a gap of a few percent in performance, power, or area is “splitting hairs,” and that being on time with yields supporting rapid ramps matters more. He says a technology includes more than one transistor type: low-leakage and high-performance transistors, SRAM, analog, and RF. He disputes Dwarkesh’s cited benchmarking of 14A against N2 without offering a different density figure in the transcript. Dwarkesh cites TSMC shipping upwards of 3X Intel’s leading-edge wafers and spending around $50 billion on CapEx versus Intel’s roughly $20 billion; Ranade calls the comparison somewhat unfair because TSMC is a foundry for many customers while Intel is largely a foundry for itself.
• Ranade says about 80% of a fab’s cost structure is fixed, so extra utilization, output, and yield can greatly improve the economics of the same footprint. He says there are three foundries left at the advanced node, compared with about 20 foundries 40 years ago. On Intel’s DRAM and flash exits, he says there were good reasons at the time and nobody could have foreseen the enormous demand; today, he says, the supply crunch is larger for memory than for compute.
• Ranade says fab costs have been doubling every four to five years, and that a High-NA scanner with associated equipment costs around $400 million. He asks whether the rising cost of patterning can continue at that rate and raises clean-slate questions such as, “Do you really need a clean room today?” He says no incumbent would willingly run the proposed hamburgers-and-cigars experiment. He adds that some CPU-design practices may also be locked into approaches established 30 years ago.