When AI Starts Designing Chips—A Conversation About EDA and Chip Design in the AI Era
Summary
- EDA generates about $12.9B a year—just 1.6% of the $800B semiconductor market—but it is the software platform chip design cannot do without. 严华 compares EDA to Word/WPS for writing or an IDE for programming, and validated IP to reusable paragraphs: the tool disappears from the finished product, but the design process cannot function without it. Synopsys has held roughly 40%–50% of the global EDA market for years, making the industry highly concentrated.
- Chip customers are expanding from specialist design houses to automotive, cloud, internet, model and other systems companies, while project timelines have compressed from 24–36 months to 12–15 months. Tesla, Meta, OpenAI, ByteDance and Alibaba have entered the market, and customers now need not just tools but also IP, methodology and white-glove support; automotive chip cycles have been compressed to roughly 7 months.
- The case for an in-house chip starts with the economics, and AI inference is one of the clearest use cases. Once team, design and tape-out costs are included, 严华 estimates that the main processor for a robot vacuum could cost several hundred million dollars. AI companies may turn to ASICs for inference as GPU procurement, electricity, cooling and infrastructure costs rise. 严华’s analogy: a general-purpose chip is like “clothes for a warhorse”—anyone can wear them, but they may not fit.
- For now, AI is mainly helping chip engineers with repetitive searches and design operations, not replacing EDA constraints, verification or final sign-off. Synopsys moved from reinforcement learning in 2020 to Copilot in 2023 and then to nearly 30 Agents; the full design flow now has more than 30 Agents, and more than 30 customers globally should already be testing them. 严华 believes humans may still be needed for final sign-off.
- Agents are forcing EDA vendors to rethink both pricing and delivery. Possible models include Token, usage-based pricing and Result as a Service, but charging by Token is difficult when customers deploy open-source models locally. The more certain shift is that FDEs will matter more, connecting Agents to each customer’s distinct workflows, data and environment.
- EDA’s incremental value comes more from chip and system complexity than from project count alone. Repetitive MCU projects built with the same methodology may add little software value; multi-die designs, chip stacking, power and thermal management, packaging and system simulation will create new demand. After acquiring Ansys, Synopsys wants to move from Silicon to systems, while Nvidia has built a broader ecosystem around CUDA, networking, storage and more.
- “AI-designed chips” remains mostly a collection of narrow automations and experiments; no end-to-end, fully unmanned tape-out has yet been demonstrated. The Samsung 3nm case involved reinforcement learning only, Qimeng-1 completed tape-out but occupied roughly 10x the area of Intel 486, and the back end of OpenAI’s “Pepper” project was handed to a design-services company and Broadcom. Model capabilities are changing quickly, so a new benchmark could emerge within 3–6 months, but the direction remains hard to predict.
Deep dive
1. EDA Is the Semiconductor Industry’s Smallest Yet Hardest-to-Bypass Design Entry Point
严华’s first analogy is straightforward: EDA is like Word or WPS for writing, or an IDE for programmers. Once a chip is built, nobody knows which tool designed it—it “disappears at that level”—but the design process cannot operate without the platform.
IP is like a paragraph that has already been written and validated. If an interface has successfully taped out on another chip, a customer can reuse it in a new design and focus its effort on the proprietary core. High-speed interfaces such as USB are examples of these reusable modules. Whether the finished product is a “Nobel Prize paper” or an ordinary newspaper article ultimately depends on the chip designer, not the EDA tool.
Global EDA revenue is about $12.9B a year, versus roughly $800B for the semiconductor industry; EDA accounts for only about 1.6%. Synopsys holds roughly 40%–50% of the EDA market. The gap between it and the No. 2 player is not large, the No. 3 player may have around 20%, and the industry is highly concentrated.
2. System Companies Enter Chips, and Delivery Speed Changes First
Historically, customers were mainly specialist chip companies such as Qualcomm, Philips in its early days and NXP. In recent years, system companies including Tesla, Meta and OpenAI, along with ByteDance and Alibaba in China, have entered the chip business, expanding the customer base beyond dedicated chipmakers.
The hard change brought by these new customers is the timeline. Traditional chips typically took 24 or 36 months from design to tape-out; 12–15 months is now common. 严华 also said automotive chip cycles have been compressed to roughly 7 months, meaning tools, IP, verification and external services all have to compress the schedule together.
The service model is changing as well. Traditional chip companies usually ask questions when they encounter problems using a tool. New system companies want “nanny-style” support: even after hiring a professional team, they remain understaffed and want Synopsys engineers directly involved in the project. With support lasting long enough, those engineers may eventually be hired by the customer.
3. In-House Chips Have No Romantic Narrative: Start With Procurement, Power and Scale
严华 reduces the decision to “an economic ledger”: in-house design only makes sense when the total cost of buying a general-purpose chip exceeds the cost of building one, and demand is stable enough. For a robot vacuum, sensor-data processing, control, heat and low power all have to be solved together. Including the team and tape-out, 严华 estimates the project could cost several hundred million dollars.
AI divides that ledger into training and inference. Training requires large volumes of data processing and compute, where Nvidia chips may be a better fit. Continuing to use general-purpose GPUs for inference, however, raises chip procurement, electricity, data-center cooling and infrastructure costs, potentially pushing companies to develop inference ASICs.
The key question is not simply whether an inference chip exists, but whether an off-the-shelf product fits the company’s own algorithms. 严华 explains it with “clothes for a warhorse”: anyone can wear them, but they may not fit. Hardwiring a company’s inference algorithms into silicon allows it to optimize for targets such as security and power consumption.
4. Mature IP Turns High-Risk Interfaces Into Reusable Building Blocks
High-speed interfaces were often designed in-house by chip companies. But a new interface cannot be taped out together with the full chip without validation; it usually has to undergo a separate trial tape-out first. Synopsys provides interface IP that has already taped out successfully, turning a high-risk step into a reusable building block.
Customers can therefore assemble mature modules such as USB and focus their effort on the proprietary core. Lowering the barrier does not make chip design simple; it reduces the amount that must be validated from scratch and raises the odds of a first-pass tape-out succeeding.
Chips do not iterate as quickly as software. If a software release contains a bug, another version can ship the next day. If a chip’s mask or layout is wrong, the chip cannot be recovered; the masks have to be remade. 严华 says failed tape-outs and delays for smartphone and automotive chips have become much less common in recent years as IP and tools have been adopted more widely.
5. The Chip Industry Only Began Cautiously Adopting AI After 2020
The issue was not a lack of demand for efficiency, but the industry’s extremely low tolerance for error. Software can ship with bugs; a chip error can make the entire chip unusable and, in severe cases, push a company toward bankruptcy. AI systems that hallucinate have to coexist with delivery targets that permit virtually no error.
Starting in 2020, Synopsys introduced reinforcement learning and related capabilities into selected parts of the flow, allowing AI to help engineers escape tedious trial-and-error work and search repeatedly for better answers. AI’s initial role here was a search and efficiency tool—not an unvalidated designer making decisions about the final layout.
A typical search target is PPA: performance, power and area. The three trade off against one another. Wider wires may improve signal transmission but increase area; thinner wires may reduce area but raise resistance and potentially power consumption. AI can explore the combinations, while the engineering system constrains and validates the answer.
严华 also draws a sharp distinction between digital and analog design. Digital design starts with languages such as Verilog and moves through logic gates to layout. Analog design starts with schematics for components such as capacitors and inductors and moves directly into layout, often relying heavily on manual drafting. The two flows only converge later in mixed-signal chips.
6. Agents Can Operate Tools, but Tools Hold the Industry’s Guardrails
庄明浩 compares the process with GPT-6 operating Blender for 3D design. A model can theoretically generate the result directly, but the outcome may be better when it operates mature software. 严华’s explanation is that Agents have open-ended generation capabilities, while tools encode the formulas, rules and constraints accumulated by the chip-design industry over many years.
Every stage has to pass tool-based validation and turn the light “green” before the error rate is low enough. Agents can generate software or chip code and invoke the design flow, but those validations remain necessary. In 严华’s view, the tools are part of the Agent’s harness, not an obsolete interface that can simply be removed.
He uses the example of a “little lobster” transferring money to show that handing an Agent unlimited permissions does not ensure good behavior. In chip design, a loss of control could destroy an entire design cycle and tape-out.
7. More Than 30 Agents Are Learning at Customer Sites How to Write “This Article”
Synopsys has developed nearly 30 Agents, while the full chip-design process has roughly 30-plus Agents handling different functions. More than 30 customers globally should already be using or testing them with Synopsys. 严华 calls the Agents “silicon-based employees”: they have been trained inside the company and understand Synopsys’ tools and capabilities.
Once deployed in a customer environment, however, the Agents still lack the customer’s business context and data. They know what Word can do, but not whether the customer is writing an argumentative essay or a narrative. Each company has different chip objectives, design environments and handoffs, so the Agent has to learn the context on site before it can progress from following detailed instructions to hearing only the objective and selecting the workflow itself.
The product roadmap has gone through 3 stages: reinforcement learning handled local searches in 2020; Copilot connected to a knowledge base in 2023 to help customers deal with Warnings and Bugs; and Agents then moved on to executing design tasks. 严华 said that once Copilot took over this work, AI had enough bandwidth to move into FDE.
8. EDA Pricing Is Moving From People to Work and Results
Legacy licenses assume that people operate the tools. But “a carbon-based employee working 996 has to go home and sleep, while a silicon-based employee can work 24 hours a day, 7 days a week.” As Agents use the tools more frequently, seat-based pricing may increasingly fail to reflect the value delivered.
严华 suggested possible models including Tokens, actual usage and “Result as a Service.” The difficulty is that Agents have different levels of efficiency: for the same task, one customer may use only a few hundred Tokens while another consumes tens of thousands. Charging by Token does not necessarily mean charging by value.
Many open-source models in China can be deployed locally, meaning the vendor may not collect Token fees. If customers run chip Agents on their own clusters and models, how to charge and how to measure the result remain open questions inside Synopsys, with no ready answer.
The more certain shift is that FDEs will become more important. The interaction between a customer’s first and second steps may differ from the next customer’s, so an Agent cannot be deployed as one standardized package. The vendor has to connect the Agent, tools and the customer’s methodology into a functioning chain for each environment.
9. After the Growth Spurt, Customers Start Asking About ROI and Value for Money
严华 observes that new customers and projects drove software demand higher over the past few years, but the trend has recently begun to flatten, possibly because “everyone who was going to come in has come in.”
庄明浩 places this in the broader AI cycle. From late 2022 and early 2023 through 2025, the industry’s strategy was almost exclusively to “spur the horse and charge ahead.” He then said that “by 2022,” whether proactively or reactively, vendors seemed to have started thinking about value for money, ROI and the scale of capital required.
庄明浩 cited Zhihu’s 5.3 Flash, StepFun’s 5 Pro Preview and Xiaomi’s model launch, which showed the Pareto frontier between unit Token pricing and model performance. He also mentioned GPT-6’s Soul and Luna [?], as well as OPPO S5.5 [?], arguing that these products were not simply chasing maximum capability but also considering value for money.
严华 sees one wave of hard-tech development after another, from commercial space, rockets, electric vehicles and robots to AI models. Previously, people may have started projects in a rush; pursuing value for money now may be better for long-term development. 庄明浩 cited the joke that “Tokens got too expensive, so we hired the employees back,” illustrating that automation is not automatically cheaper than labor.
10. Complexity, Not Chip Count, Is What Really Drives EDA Value
Synopsys’ business model shows that more projects do not necessarily mean more revenue; complexity and customization determine software value. Building 20 MCU products with the same methodology may require exactly the same tools, even if chip shipments are large. The parties making the real money may instead be packaging and testing companies and manufacturers such as TSMC and Samsung.
New demand comes from designs that existing tools struggle to cover. The program cites Huawei’s “throwing law” and TSMC’s SoIC as examples: interconnects between multi-die packages can become too long and constrain performance, prompting designers to fold or stack chips. Stacking, however, makes heat dissipation a much more serious problem.
That is the logic behind Synopsys’ ambition, after acquiring Ansys, to move “from Silicon to systems.” Controlling heat in a single die is only the first step; dissipating it through liquid nitrogen, air cooling or natural cooling requires system-level simulation of the chip, package and complete machine together.
Nvidia is presented as a model of systemization. 严华 emphasizes that CUDA remains the core ecosystem, while also pointing to the integration of solid-state, optical, network-transmission and storage equipment. 庄明浩 adds that a standardized full system could be transferred to another customer even if the original customer went bankrupt. Its value is no longer limited to an isolated chip.
11. Copper, Thermal Management and System Simulation Are Redrawing the Chip Boundary
严华 identifies thermal management as the central problem in today’s AI infrastructure: as compute rises, cooling requirements rise with it. The program discusses ideas such as putting data centers in the sky or carrying them on ships at sea; 庄明浩 asks how heat would be removed in the sky, where there is no air.
Silicon photonics is discussed as a way to transmit signals optically across silicon and reduce the heat generated by copper. As relayed by 严华, Jensen Huang has also described copper wiring as one factor limiting AI’s continued development. The next round of tool demand will therefore span electrical, optical, thermal and mechanical structures.
System companies develop their own chips not only to chase peak performance, but also because their algorithms may run at lower power on customized silicon, reducing cooling requirements. The weights assigned to cost, performance, power and security differ by customer; there is no general-purpose chip that solves every problem.
12. Fully Automated Chips Have Not Arrived, but Headcount May Fall
In response to companies claiming that embedding EDA tools into Agents eliminates the need for standalone EDA tools, 严华 asks whether the answers produced after internalization still follow the original formulas and logic, and whether they contain hallucinations. His view is that Agents will play a larger role, but final sign-off may still require people because an Agent will not be held responsible when a chip fails.
Samsung’s 2021 3nm case involved reinforcement learning in only part of the flow, not independent AI design. A related Nvidia project used AI to generate some code but still depended on verification scripts and logic-tree validation written by model engineers. AlphaChip’s public case also faces replication questions: Google published the weights, but it remains uncertain whether the result can subsequently be reproduced.
The Institute of Computing Technology at the Chinese Academy of Sciences taped out “Qimeng-1” in June 2023 on a 65nm process, using a fully automated AI flow, the open-source EDA tool OpenROAD and the BSD algorithm cited by the program. It bypassed the conventional Verilog-to-netlist process. The chip used roughly 4 million logic gates, versus about 400,000 for Intel 486, and its post-tape-out area was roughly 10x larger. It looked more like an experimental demo than a design with practical value.
In 2023, VeriCall claimed it could generate GDS from 219 characters with no human involvement, but it used only a virtual standard-cell library and could not tape out a real chip. OpenAI’s “Pepper” project handed the subsequent work to a design-services company and Broadcom, with OpenAI mainly responsible for the earlier schematic portion. A tape-out completed with no human involvement from start to finish has therefore still not appeared.
Headcount may fall first. 严华 believes a simple chip might eventually be completed by 2 or 3 people. Zeku had 3,000 employees at its peak, including roughly 1,500 working directly on chip design; that heavy investment was also tied to its effort to minimize IP purchases and build much of the stack itself. If a company uses mature IP and outsources the back end to a design-services firm, a relatively frugal automotive chipmaker might complete a project with 200–300 people.
严华 also rejects overly confident forecasts. When Synopsys built Copilot in 2023, different models still showed widely varying answer accuracy, yet within a short time almost all models became usable. Models are developing quickly, and a new benchmark may appear within 3–6 months, making the current trajectory difficult to predict.
People still have to decide what kind of chip to build, especially at the top-level architecture. The relevant talent today still comes mainly from integrated circuits, communications, electronics and other technical disciplines. In the future, cross-disciplinary knowledge, creativity and the ability to express requirements precisely in natural language may matter more.
At the other end of the stack, some tools designed for humans may disappear. Waveform-visualization tools allow people to find model problems by inspecting waveforms; in the future, Agents may communicate directly with one another, eliminating the need for people to inspect waveforms. 严华 stresses that this does not mean every tool can be replaced. The question is whether to return to first principles and determine what is actually needed in the middle of the flow.