Two Chip Engineers' EDA Primer: AI, Moats and the $35B Mega-Deal
Summary
EDA determines whether a chip can be built, how well it performs, and how quickly it can be produced—and directly affects performance, power, area, and reliability. As designs have grown from thousands of transistors to tens or hundreds of billions, humans can no longer complete them manually; engineers cannot touch the physical chip before tape-out and must rely on EDA feedback for functional and physical information. EDA is therefore both “the chopsticks we eat with” and the behind-the-scenes force defining the ceiling for every electronic product.
EDA is a “picks-and-shovels” business with low distribution costs and exceptionally sticky customers, but it cannot share in the upside when chip volumes scale. Licenses can be perpetual, annual, or usage-based, with fees also tied to functionality and user count; even during semiconductor downturns, EDA remains a difficult-to-cut fixed expense—a “rain-or-shine” business. But when a customer’s shipments rise from 10M chips to 100M, EDA vendors typically still earn only design-stage revenue rather than “the gold money” from mass production.
Verification accounts for roughly 70% of the labor and time in a chip project, while EDA and verification workflows help eliminate errors before tape-out risks an investment worth hundreds of millions of RMB. Tens or hundreds of thousands—or even millions—of lines of code must meet targets for functional, state-machine, branch, and code coverage, while a single large test case can take 30 minutes to an hour to run. The “10x rule” means bugs become more expensive to fix the later they are found; once a product is in phones, computers, or cars, the cost can escalate from masks and recalls to the “cost of trust.”
EDA’s core moats are large-scale algorithms, tight coordination with wafer processes, and a production-proven ecosystem, together forming a barrier against risk. If the same Verilog produces a netlist with 20% more area after synthesis, costs could rise 20% outright. Faced with chips that have already absorbed tens of millions to RMB1B in investment, customers would rather use a mature flow where “when something goes wrong, the tool is not the first thing they suspect.” Even capable domestic vendors struggle to dislodge the incumbent tools used for mainstream large digital chips.
AI and EDA are mutually reinforcing: AI chips are pushing design complexity to the limit, while AI is compressing parts of verification and place-and-route from weeks to days or even hours. Clock-domain-crossing issues can fall from 2 weeks to 1 month to 2 or 3 days, while 6 hours of AI-driven place-and-route can match the output of a senior expert working for 2 or 3 weeks. But the guests believe AI remains strongest at “single-point optimization”; SoC-level coordination, sign-off accountability, and confidentiality requirements mean experienced engineers cannot yet be replaced.
AI is more likely to reinforce the data and ecosystem advantages of the Big Three first, because Verilog, SystemVerilog, and UVM corpora are precisely the core IP customers are least willing to expose. General-purpose models can generate usable Python, but commercial-grade Verilog generation remains “very poor,” making lack of training data the first obstacle for startups. Players such as Synopsys, Cadence, and ARM, with accumulated EDA or IP assets, are better positioned to post-train models and embed the capabilities into existing tools; customer code, however, is protected by confidentiality agreements and cannot automatically become training data.
Synopsys’ $35B acquisition of Ansys is aimed not at adding another tool, but at linking chip, package, thermal, electromagnetic, and system simulation into a collaborative platform. Looking toward 2026–2036, 程曼祺 places greater weight on system-level coordination, while Very老哥 is betting on AI lowering labor and iteration barriers. Both views point to the same shift: Chiplet, 2.5D/3D packaging, and full-stack hardware-software integration are moving the unit of competition from a single chip to the entire system.
Deep dive
1. EDA Turns Tens of Billions of Transistors into a Manufacturable “Electronic Skyscraper”
秋豪 explains EDA through the metaphor of a skyscraper: a brilliant architect and reinforced concrete are not enough; you also need scales, calculators, and construction drawings. EDA answers 3 questions—“Can it be built, how well can it be built, and how fast can it be built?”
In the 1980s, hundreds or thousands of transistors could still be drawn by hand. Today’s chips have reached the tens- or hundreds-of-billions scale, making it impossible for humans to turn design concepts into precise layouts. Very老哥 puts it more directly: “EDA is the chopsticks we eat with,” as indispensable as a steering wheel when driving.
Performance, power, and area determine speed, energy consumption, and cost, while reliability extends all the way to automotive safety. 秋豪’s summary: “We cannot see EDA, but these tools define the ceiling for every electronic product behind the scenes.”
2. Architecture, Verification, and Back-End Design Build Houses in a Data World
Architecture design is like agreeing on a renovation checklist with the owner: the number of rooms and living areas map to core count and cache; water, electricity, and network capacity map to bus bandwidth and memory interfaces; whole-home automation maps to dedicated accelerators. Adding a gym later is like adding an AI or ISP module.
Verification is not inspecting a finished house. It is simulating a flooded bathroom, an overloaded circuit, or even an earthquake inside EDA to confirm functional, structural, waterproofing, and safety constraints. The back end then handles place-and-route, clock-tree interference, signal crosstalk, and DRC—like arranging furniture and wiring while managing tile gaps.
Very老哥 specifically corrects the “renovation” analogy: until architecture, verification, and back-end design are complete, engineers still have only data files. “All the design work is done without touching the final physical chip.” Only after the files are handed to a foundry is the building actually manufactured.
3. When Chip Design Is Complete, the Project Is Often Only 30% Done
Very老哥 breaks down the bulk of NRE into IP purchases or development, back-end design, and tape-out masks. Purchased IP shows up as price; internally developed IP shows up as engineer-months—for example, 20 engineers working for 1 year equals 240 engineer-months.
Design completion typically represents only about 30%; the remaining roughly 70% lies in verification. From hundreds of thousands to several million lines of code must be covered line by line, while functional, state-machine, branch, and code-coverage metrics must all meet requirements before sign-off.
VIP, or Verification IP, is a key asset for shortening verification cycles. CPU, high-speed interface, and I/O modules can be purchased, while the verification team can reuse mature capabilities through VIP and UVM methodologies. A large project’s single test case may take 30 minutes or even 1 hour to run, so shaving time off one run compounds across thousands of iterations.
4. Test Costs and the “10x Rule” Make Reliability a Hard Constraint
文哥 adds that DFT and testing are also expensive. At a typical large company, every 10 design engineers may be supported by 3 or 4 design-for-test engineers, followed by testing to determine whether manufacturing defects have appeared across tens or hundreds of billions of transistors.
Chips must go through ATE machines both as wafers and after packaging. ATE is not as expensive as a lithography machine, but buying several additional testers can approach the cost of 1 lithography machine. Smaller companies often have to rent them at $100–$200 per hour, making test speed a direct determinant of time to market.
The industry’s “10x rule” means a bug is cheapest to fix during design; correcting it after tape-out can cost 10x more. If the chip has already entered customers’ phones, computers, or cars, the cost is not just potentially tens of millions in masks and recalls, but also the loss of trust and reputation.
5. EDA Is a Good Business Because Customers Cannot Afford to Fail
A software license can be delivered to 1, 10, or 1,000 companies with little difference in distribution cost. Unlike chips, which incur manufacturing costs with every unit sold, this gives EDA resilience across the cycle—what 秋豪 calls a “rain-or-shine” business.
But customers will pay only if the tools can support stable mass production. Very老哥 gives the scale relationship: a customer may spend $1M on tools to support a $100M chip project. EDA vendors must provide enough justification to win the customer, or software risk becomes project risk.
The business also has a ceiling. A chip company may ship 10M or even 100M units, while the EDA vendor typically does not share in final-volume revenue. As Very老哥 puts it, EDA earns “picks-and-shovels money during the design stage,” not the gold money from mass production.
6. Licenses Smooth Revenue but Turn Costs into Fixed Expenses
The guests describe several common models. Perpetual licenses create the greatest upfront cash burden but can be amortized over time; annual subscriptions create a middling burden but become difficult to cut during industry downturns; usage-based pricing minimizes the initial burden but can run out of control when a new project suddenly increases compute demand.
Actual pricing is also broken down by functional module, license count, and number of users. Opening a GUI for 1 person is not priced the same as having 100 people use it simultaneously. Very老哥 says time-based licensing is common: vendors provide a feature list, and customers select what they need and renew annually.
7. The First Customers for Domestic EDA Startups May Not Be in China
程曼祺 shares a counterintuitive finding from one survey: early customers for domestic EDA startups were mainly Silicon Valley startups rather than small Chinese chip companies. Large Chinese customers have ample budgets and can directly buy mature tools from Cadence or Synopsys; some smaller customers have weak willingness to pay and may even turn to pirated software.
This leaves domestic startups facing a double bind: large customers do not want to bear the project risk of switching tools, while small customers may not be willing to pay. Silicon Valley startups, by contrast, may bring only small orders but can provide the real customers and revenue needed during the early stage.
Pirated software is not a complete substitute either. 秋豪 points out that foundries including TSMC, Samsung, Intel, GlobalFoundries, and SMIC certify only a limited number of EDA flows. With uncertified tools—or even data generated by pirated tools—a foundry may refuse tape-out.
8. Three Layers of Moat Make Advanced-Node Migration a Long-Term Contest
文哥 divides the barriers into 3 layers: algorithms must handle physical simulation and computational-science problems; tools must remain tightly coupled to foundries’ new processes and continuously update design-rule libraries; and the complete tool chain must cover design, simulation, verification, and testing, creating high switching costs.
Moving from 28nm to a more advanced node is not a matter of simply changing parameters. It may require major restructuring of algorithms, scripts, and tool internals. A tool that fails to keep pace with process technology can be eliminated. The other side of the “rain-or-shine” business is the constant pressure of semiconductor advancement.
秋豪 believes the deepest challenge remains algorithms. A design with 100 gates may converge easily, while designs with 1B or 10B gates can leave even mature tools “stretched to the limit.” New entrants must produce the right answer within acceptable time and resource constraints, and the difficulty rises nonlinearly.
9. Comprehensive Tools First Ensure Correctness, Then Determine Competitiveness
The path from Verilog to netlist looks like only the first step, but large chips often need to be split into hard blocks for separate synthesis before being integrated at the top level. Tools must handle enormous numbers of gates and macros or they cannot process the full design at all.
Correctness can be checked with tools such as formal equivalence, but “optimality” depends on power, area, gate count, and back-end routability. If one tool generates a netlist with 20% more area from the same code, 秋豪 believes costs could rise 20% outright.
Customers therefore do not lightly risk a new tool. The larger the chip, the more uncontrollable variables it contains, and the more the project depends on production records to provide certainty from the outset. The real value of mature tools is letting engineers focus on their own circuitry—“when something goes wrong, they do not suspect the tool.”
10. AI Chips First Create a Complexity Inflation Shock for EDA
Next-generation compute chips increasingly use 2.5D packaging, while 3D compute chips stacked through TSVs are also under discussion. EDA must cover the full flow for multiple chiplets, from design and simulation through mass production, creating new scale and process challenges for traditional tools.
An accelerator for a model with hundreds of billions of parameters may integrate tens or even hundreds of billions of transistors. Huge netlists can make traditional place-and-route extremely slow, cause crashes and restarts, or become impossible to process. AI is therefore expanding the EDA market while forcing tools to rewrite their scale limits.
Very老哥 reinterprets AIGC as “AI-generated chip”: AI first generates Verilog, then drives automation through netlist, GDS, and eventually production. His long-term vision is that AI could span “the entire life cycle of a chip, from birth to death.”
11. AI’s Transformation of EDA Will Move from Immediate Pressure to Long-Term Coevolution
文哥 divides the process into short, medium, and long terms. The short term brings an immediate rise in complexity; the medium term brings AI into deeper EDA workflows; and the long term is “coevolution between AI and EDA,” with chips providing AI compute and AI improving chip design in return.
He says coevolution requires 3 breakthroughs: training latency and other prediction models on massive process-library data; deeply integrating chip-level and system-level tool chains; and earning customer trust by ensuring confidential data is not exposed through model training or real-time interaction.
Synopsys’ DSO.ai is cited as a real-world example. According to 文哥, it is already used by a number of companies to improve performance, power, and area—PPA—while completing design faster and entering production earlier. 程曼祺 adds that training data may help engineers generate new design ideas, and real-time dialogue can sometimes be faster than submitting a case and waiting for an EDA vendor to respond.
12. Weeks of Work Are Being Compressed into Days or 6 Hours
秋豪’s first data point comes from clock-domain-crossing analysis. There may be up to millions of issues, and traditional processing can take 2 weeks or even 1 month; with AI assistance, the task may be completed in 2 or 3 days.
The second example comes from back-end place-and-route. AI can reach in roughly 6 hours the level that an expert with 10 to 15 years of experience might take 2 or 3 weeks to achieve. The value is not just labor savings, but faster PPA convergence and a shorter time to market.
秋豪 believes a chip may already have absorbed RMB100M in investment, making the avoidance of failure more important than the cost of saving 1 expert. AI is better suited to general-purpose work, while final sign-off still requires internal and external experts to “hunt for bugs” together.
13. Engineers Will Not Be Replaced by Tools, but They Will Have to Change Interfaces
The host asks: if AI can match a senior place-and-route expert, will the expert be replaced or simply have an easier job? 文哥 believes less-experienced roles are more exposed, while the judgment and accountability carried by experienced engineers are difficult to automate.
秋豪 goes further: engineers used to operate EDA directly, but are now beginning to operate the AI capabilities inside EDA. The knowledge system has not changed; it is still a tool—just “a more obedient tool.”
文哥 believes AI is currently very strong at single-point optimization but lacks the SoC-level system-optimization capability of the world’s top chip companies. Strong engineers therefore cannot merely know how to invoke tools; they must understand, use, and even develop AI, turning experience into an internal company capability.
14. Scarce Verilog Data Means the AI Upside Will Initially Flow to Incumbent Giants
秋豪’s practical observation is that general-purpose models can often generate Python that runs directly or needs only minor modification, while Verilog generation is “very poor.” To enter chip design, models still need post-training on Verilog, SystemVerilog, SV, UVM, and related corpora.
The companies with the most data are often those that already own IP or EDA assets, such as ARM, Synopsys, and Cadence. A chip company’s GPU and SoC code is core IP; even when it works with an EDA vendor, confidentiality agreements prevent that code from being used to train a large language model.
Domestic AI startups are already attempting Verilog generation, but their first obstacle is “having no corpus.” Even if a model can write only 80% of a module for an engineer, that already has commercial value. But in 秋豪’s view, such companies may eventually be acquired by large EDA vendors.
15. The EDA Big Three Are the Product of 40 Years of Specialization and M&A
In the early days, IDMs such as Intel developed internal tools for their own processes. After the foundry model emerged in the 1980s and semiconductor specialization deepened, independent IP and EDA companies gained room to scale. 程曼祺 also notes that Dr. Aart de Geus advanced logic-synthesis technology and founded Synopsys in 1986, helping move chip design into the automation era.
The guests review the founding dates of Mentor around 1981, Synopsys in 1986, and Cadence around 1988. These companies grew alongside personal computers, CPUs, and the golden era of US semiconductors. Nearly 40 years later, Synopsys has been in China for almost 30 years.
Based on his own incomplete statistics through 2022, 文哥 says Synopsys had acquired more than 100 companies in total—around 3 per year on average. It was “either acquiring, or on the way to acquiring,” with much of the apparently native full-flow capability seen today actually assembled through long-term M&A.
16. The Big Three Never Merged Because EDA Is Dozens of Businesses
秋豪 points out that a single company may use dozens of EDA tools at once: VCS for simulation, Design Compiler for synthesis, Formality for formal verification, ICC2 for back-end design, and PrimeTime for timing sign-off. Digital, analog, and RF design each have their own independent methodologies.
Asked why there is no monopolist, 文哥 responds with a Zhihu meme: “First ask whether it is true, then ask why.” The top 3 or top 5 players controlling 70% to 80% of the market is already an oligopoly. But the remaining niches continue to produce point opportunities as new processes and use cases emerge.
17. The $35B Acquisition Shifts Competition from Chips to Systems
After Synopsys completed its $35B acquisition of Ansys, it could connect chip design with mechanical, thermal, electromagnetic, and package simulation, enabling coordinated optimization from chip to system and from design to physical fields.
秋豪 believes the deal not only fills capability gaps but also inherits Ansys’ ecosystem position among foundries and across the supply chain. Rather than developing everything from scratch, a single acquisition can provide faster access to certifications, customer relationships, and new markets such as automotive and aerospace. 文哥 emphasizes that it helps connect the full chain from chip to system.
As a tool user, 秋豪 believes integration can improve efficiency, but candidly admits: “From one angle, we actually do not want to see an oligopoly,” because deeper full-flow integration also raises switching costs and supply-chain dependence.
18. Domestic EDA’s Realistic Opportunity Starts with Point Tools, Not Full-Flow Mainstream Chips
Both guests give the same direct answer: they currently do not use domestic EDA in their work. 文哥’s international employer lacks the motivation to adopt it, while Very老哥’s domestic chip company does not want its projects to bear the opportunity cost of an unfamiliar tool—“No one wants to take that responsibility.”
More viable entry points are niche segments such as analog, RF, modeling, or parameter extraction. An LDO, for example, may contain only a dozen or so transistors, with the core task being to optimize transistor width-to-length ratios. A clearly superior point tool can win customers without first solving the full-flow challenge for large digital SoCs.
Very老哥’s path is to “become unassailable” in a niche, build a real customer base, and then expand through R&D or acquisitions. 文哥 also stresses that even the Big Three, despite having full-flow capabilities, are not the best at every individual tool stage.
19. 600–700mm² Chips Turn Runtime into a Capital Cost
文哥 observes that AI compute chips often reach roughly 600–700mm² per die. The larger the chip, the slower the EDA iterations. 秋豪 adds that manufacturing yield is also harder to control for large chips, putting design, production, and tools under simultaneous pressure.
Chip investment can range from tens of millions to RMB100M, and reach RMB1B. A 1-day delay to market not only postpones revenue; the cost of capital also matters. EDA’s key task is therefore to shorten every iteration so complexity does not break the time-to-market and commercial feedback loop.
20. Smartphones, Cloud Computing, and Cars Set Three Different Exams for EDA
文哥 says smartphones care most about PPA, especially power and area. 秋豪 adds that smartphone chips have the “most complex power-domain partitioning, bar none”: when the screen is off, large numbers of modules are completely powered down, leaving only a minimal core running, while clock gating, power-down, and dynamic voltage scaling are also required.
Cloud computing pursues large-scale compute. EDA must divide layouts and routing at the 1B-, 10B-, or 100B-transistor scale into parallelizable subtasks while controlling clock-tree skew, preventing synchronization failures across cores from dragging down compute utilization.
Automotive electronics puts reliability first. Vehicles may operate for 10 to 20 years; chips must withstand environments from roughly −30°C to 70–80°C, while controlling aging, modeling error, and single-point failure rates and passing relevant certifications.
The corresponding solutions include fault injection to accelerate automotive-grade verification and thermal-coupling simulation from chip through package to cooling, exposing hotspots early. Beyond shared PPA requirements, each end market requires EDA to understand the product context rather than merely complete circuit calculations.
21. Developer Conferences Are Both Product Feedback Loops and Gateways to Chiplet Standardization
秋豪 views developer conferences as cross-company clearinghouses for problems. A vendor may not act immediately when 1 customer requests a feature, but if several companies submit similar cases, the request may drive a new capability. The following year, customers may bring their own innovations back to the conference to share.
Very老哥 is most interested in Chiplet solutions. Constrained by single-die area and compute demand, multi-chiplet designs are increasingly viable, but interconnects, UCIe, IP, and EDA flows are not yet fully standardized. Large EDA vendors have both the industry standing and the incentive to push standards that could generate substantial returns.
22. The 2025 Industry Keywords Are Compute, Stabilization, AI, and Heterogeneous Integration
Very老哥’s 3 words are “compute, stability, AI.” Domestic investment is concentrated in GPU- and TPU-like compute chips; failures continue, but new companies are still being created and the industry is stabilizing. AI is simultaneously creating chip demand and entering front-end, verification, and back-end workflows.
文哥 uses capex to illustrate AI intensity. He cites combined Q2 2025 capex of $87B for Google, Microsoft, Meta, and Amazon, a record high, with AI compute hardware now at the center of investment.
His other 2 terms are “heterogeneous integration” and “vertical restructuring.” CoWoS capacity requires a queue, while panel-level, substrate-less, and fan-out approaches are advancing in parallel. Synopsys forecast at the start of the year that 50% of new high-performance computing chips in 2025 would use 2.5D or 3D multi-chiplet designs; 文哥 believes that level could be reached by year-end.
23. The Supply Chain Is Shifting from Horizontal Specialization to Deep Integration
文哥 observes that packaging has evolved from a back-end supporting step into a performance-defining stage. Chiplet count, individual functions, and interconnect architecture must be decided when a project is initiated; heterogeneous integration is not merely a manufacturing choice but part of the architecture.
“Vertical restructuring” does not necessarily mean bringing everything in-house. Intel’s IDM 2.0 controls design, manufacturing, and packaging, while Samsung may connect data across memory, logic, and foundry operations. Fabless companies are also binding more deeply with foundries, IP vendors, OSATs, and EDA vendors to form one-stop collaboration.
This shift is tied to AI: demand is beginning to be defined in natural language, packaging is taking over from the single-chip bottleneck, and ecosystem partners are sharing more design constraints. Competition is therefore rising from an individual tool or die to cross-layer optimization capability.
24. The 2026–2036 Debate Is Whether System Coordination or AI-Driven Lower Barriers Arrives First
程曼祺 chooses “system-level coordination.” AI remains oriented toward single-point optimization in the short and medium term, while process technology is gradually approaching its limits. She advocates using coordination as the axis—linking left to materials, devices, and manufacturing; right to algorithms, frameworks, and use cases; and bringing advanced packaging, hardware-software integration, and PPA into a single loop.
Very老哥 still puts AI at the center of the next 5 years. The funding barrier will not disappear, but if AI can reduce labor and shorten verification and iteration cycles, a lean team may be able to design chips that previously required a large organization, creating more products and companies.
程曼祺 compares this with the way the Fabless model reduced manufacturing investment and enabled design companies such as Nvidia to grow. The guests do not present this as a certain conclusion, but as a prediction to watch: whether AI can lower the industry’s entry barrier again depends on when it moves from point tools to full-flow capability.
25. What Newcomers Need Most Is Not Tool Recall, but Becoming a “Knowledge Router”
程曼祺 identifies 2 key capabilities: curiosity and problem-solving. Engineers must follow new architectures, IP, tools, and verification methodologies, and take every problem through the loop of “cause—solution—why it is better—how to prevent recurrence” to grow into experts.
Very老哥 cites AMD CEO 苏姿丰’s advice and chooses “rapid learning.” The EDA, languages, and scripts taught in school may already be outdated; engineers must move from Perl to Python, learn advanced processes, and master AI. The future is not about storing knowledge, but becoming a “knowledge router” that connects fragmented information—even evolving from a tool user into an AI trainer.
Very老哥 also warns that “70% of chip design work is still very boring”—in plain terms, advanced manual labor. 文哥 then links learning agility to curiosity, arguing that engineers must embrace frontier technologies and master new tools quickly. The judgment relayed by Very老哥 is: “The future belongs to engineers who learn nimbly.”