Former Intel CEO: Why This is the Best Time to Build Hardware
Summary
AI has compressed logic design faster than it has compressed the path to deployed silicon, shifting value toward fabrication, packaging, memory, power, cooling, and rack-scale integration. Gelsinger’s diagnosis is “it’s no longer a chip, it’s a rack”: a three-month design can face nine months for silicon and another three for advanced packaging; he later described scale-up and software deployment as taking roughly 18 months—long enough for the target workload to move.
The field of roughly 100 AI processor vendors is a transitional boom, not a durable market structure. Raghu framed the number as historically unprecedented; Guido predicts consolidation because workloads will evolve beyond today’s prefill/decode specialization, successful hardware requires enormous capital and software investment, and major customers will effectively select the winners. Gelsinger agrees that consolidation is likely but argues that agent-generated optimized kernels could let some heterogeneity survive beneath software abstractions.
Memory is the most conspicuously under-innovated part of the AI stack and may finally be positioned for a regime change. After participating in five proposed architectures—including the failed Optane effort—Gelsinger counts “zero” major new memory technologies in 30 years beyond DRAM, SRAM, and flash. AI is fundamentally a memory workload, creating the capital and technical pressure for integrated memory-compute structures, new materials, and dense stackable memory. Guido points to d-Matrix, Cerebras, ferroelectrics, and other emerging approaches.
Optics should displace copper for scale-up I/O around 2028–2029, though not inside the core compute-memory complex. Gelsinger argues that it is already “more expensive to make copper work at 5 meters than to make optics work at 100 meters”; the remaining barriers are lasers, heat, packaging, and an immature supply chain rather than fundamental physics. Guido says predictable AI traffic could also favor optical circuit switching over packet networks designed for unknown destinations.
Power availability is becoming both the ceiling on AI deployment and a source of hardware investment opportunities. Raghu framed “energy capacity is equivalent to economic capacity,” describing national capacity as roughly flat for 10–15 years and likely to grow only about 4% annually, while Gelsinger cited eight-year gas-turbine lead times. Gelsinger expects energy shortages to produce more data-center project defaults, even as 800VDC distribution, vertical GaN conversion, nuclear generation, cooling, and superconducting systems attract innovation.
The next VMware-sized abstraction opportunity may be infrastructure designed for agents rather than humans. Agents need fast provisioning, security profiles, performance management, migration, guardrails, and policy enforcement—the equivalent of “vMotion for agents.” The design objective changes from abstracting hardware for operating systems and applications to abstracting hardware and operations for autonomous software, while retaining human control through constitutions, policies, and dashboards.
Deep dive
1. Intel’s 486 era joined education, production, and toolmaking
Gelsinger entered Intel at 18 after vocational school, having never flown on an airplane. Recruiter Ron Smith’s assessment—“smart, proactive, and arrogant. He’s perfect”—began a path from the late 286 team to fourth engineer on the 386 and then architect and design manager for the 486.
He pursued bachelor’s, master’s, and doctoral studies while designing chips, testing classroom ideas directly against production constraints. After a Stanford professor proposed a carry-lookahead design, Gelsinger returned two days later to say it did not work; the next two classes became a debate over why a design intended for publication failed in his 386 work.
The 486 arrived before a mature EDA industry. Intel created its own hardware-description language and compiler, then worked with Alberto Sangiovanni-Vincentelli’s Berkeley group on automated placement, routing, and timing. Raghu characterized the processor as not only a compatible pipelined chip but also part of the foundation for modern EDA.
2. AI accelerates design while exposing slower physical bottlenecks
Gelsinger sees today as another transition: AI can translate high-level goals, software layers, and kernels into Verilog with surprising ease. Analog design remains harder because the industry lacks sufficient silicon data, forcing either conservative circuits or continued reliance on difficult manual work and a small number of experts.
The new mismatch is temporal. A team might create a strong design in three months, yet silicon processing takes about nine months and advanced packaging another three. Rack-scale deployment takes longer still; Gelsinger later described scaling up and deploying the software as taking roughly a year and a half. His target is a prototype flow measured in one or two months, without a roughly $50 million mask burden.
Graphcore is his cautionary specimen: “It wasn’t a bad design, but the world had moved on.” If scaling and software deployment take roughly a year and a half, the assumptions about AI workloads that informed the architecture may already be obsolete.
Power and thermal design remain similarly primitive. Gelsinger said guard bands can consume 40% of the power envelope, while 3D tools for voltage loss and hotspots remain inadequate. AI may simplify logic, but “the bottleneck shifts to another location.”
3. Specialized accelerator abundance should give way to consolidation
Raghu framed the roughly 100 AI processor vendors as historically unprecedented. Guido predicted that the population is temporary and will narrow because scale requires winning customers, raising capital, sustaining software, and deploying whole systems—not merely producing an attractive chip. Gelsinger agreed that large consumers will help select the winners.
Guido is skeptical of architectures optimized too narrowly for prefill and decode, or for inference and verification, because nobody knows what the workload will be in two to four years. LLMs may hit limits in molecules, chemistry, imaging, and 3D modeling, while AI-guided scientific work could restore traditional HPC requirements such as 64-bit precision.
Guido argued that the eventual winners will also be selected by large workload owners. OpenAI, NVIDIA, Anthropic, and similar platforms will favor hardware and software that can co-evolve, while leveraging those platforms requires continuing investment in software and workload advancements.
Gelsinger’s counterpoint was that heterogeneous hardware used to be constrained by compiler costs, but AI changes programmability. Groq’s framing was that humans may no longer optimize the machine, while “a swarm of agents can do it overnight.” He allowed that some heterogeneity can survive beneath abstractions, but emphasized the difficulty of financing perhaps $50 billion of data centers, power, and production capacity.
4. AI creates the conditions for the first memory reset in 30 years
Gelsinger has participated in at least five new memory architectures and referred to nearly 100 industry events over the past 30 years. Asked how many major technologies emerged over three decades, his answer was “zero”: the field still rests on DRAM, SRAM, and flash, while Optane “never saw the light of day” and was ultimately killed.
The economics discouraged invention: memory might generate profit for one year and losses for the next four. AI changes the premise because “AI can be described as a memory workload,” while the three major memory vendors are now among the world’s 20 most valuable companies. Gelsinger sees that combination of capital and technical need as justification for renewed innovation.
Guido expects memory and computation to become more tightly integrated, pointing to d-Matrix and Cerebras as examples of the direction. He is particularly interested in ferroelectric or other non-capacitive materials that could yield high-performance, high-density, stackable memory, while remaining less enthusiastic about low-cost flash and MRAM-based approaches because of cell-speed and performance concerns.
Stacking has a physical sweet spot because value rises with every layer while yield requirements compound. Gelsinger favors a general stack of roughly three to five layers, with perhaps two or four memory layers—not 8, 16, or 32. Once compute tiles, power delivery, redistribution layers, optical components, and other materials are included, his standard configuration is already about eight layers: “an engineering marvel and a manufacturing nightmare.”
5. Optics belongs in I/O, not between every compute and memory element
Guido rejected optically disaggregating the core compute-memory complex: every optical-electrical-optical conversion adds cost, power use, and loss. Computation can consume femtojoules, while communication per bit can be “a thousand times worse,” making distant memory physically unattractive despite its configurability.
Guido is also unconvinced by processing-in-memory, while explicitly allowing, “I may be wrong.” PIM forces workloads into the memory architecture and imposes constraints on the workload. Gelsinger instead favors versatile, high-bandwidth memory placed close to a real compute engine as algorithms continue to evolve.
For I/O, Gelsinger’s position reverses completely: “I’m a big fan of optical communications. I believe all I/O should be migrated to optical.” Having declared copper’s end about 25 years ago, he now expects NPO, CPO, or related approaches to reach a turning point around 2028–2029. He says physics is already making copper at 5 meters more expensive than optics at 100 meters.
The NVL72 illustrates both urgency and cost. Gelsinger said it “should never have been built,” yet called it an engineering marvel that took the industry another year and a half to understand. With a mature optical supply chain, he argues, scale-up systems could deliver better power, cost, and energy efficiency.
6. AI networks will become more predictable as workload boundaries blur
Guido said packet networks were designed for traffic whose destination was unknown, whereas AI presents nearly the opposite problem: large, predictable, manageable flows. He therefore expects optical circuit switching, or a related architecture, to enter computing complexes alongside optical links.
Raghu questioned whether scale-up and scale-out are fundamentally different or merely separated by current protocols and front-end versus back-end conventions. Gelsinger expects those system architectures and protocols to converge over time.
Training and inference may converge as well. Gelsinger expects the boundary to weaken where “continuous learning is the essence of algorithms” and models update weights during inference, although he was uncertain about the precise scale implications. Guido added that smaller, dispersed workloads and differing compute-versus-bandwidth constraints may preserve some hardware heterogeneity.
7. Energy scarcity turns electricity back into a technology sector
Raghu framed the energy problem by saying that renewable additions had roughly matched coal retirements for 10–15 years, leaving total national capacity flat. He also expected only about 4% annual growth despite rising demand. Gelsinger accepted the premise that “energy capacity is equivalent to economic capacity” and argued that more capacity is essential.
Supply cannot expand quickly: Gelsinger cited gas-turbine lead times of up to eight years and the loss of a capable domestic nuclear industry. Raghu added that the United States is heavily dependent on China for renewable-energy supply chains. Without electricity, Gelsinger asked, “what’s the point of building a new data center and buying millions of GPUs?”
Gelsinger expects power shortages to become a headwind and produce more data-center project defaults, identifying Oracle’s comments as an early signal. The pace of AI investment need not collapse, but investors and operators will increasingly test whether announced GPU and construction commitments have credible energy behind them.
Inside the facility, 800VDC—“Edison’s revenge”—could eliminate conversion stages. Guido highlighted vertical GaN capable of stepping directly from 800 volts to 48, 12, or 5, alongside solid-state transformers and switches. The discussion also covered cooling, refrigerants, and the possibility that Snowcap’s superconducting approach could improve power performance by 1,000 times.
8. Agent infrastructure revives VMware’s abstraction thesis
Gelsinger’s broader rule is that every major innovation creates a new abstraction layer. VMware managed workloads, networks, storage, and systems; the corresponding AI question is who manages groups of agents, their security profiles, performance, and other operational requirements.
An agent-oriented VM would differ from a human-facing one because “humans are far more patient than agents.” Provisioning and startup must be faster, while migration, safety, performance management, and hardware abstraction become native services—summed up as “vMotion for agents.”
Humans still need to define constitutions, guardrails, policies, and dashboards. Neither side is sufficient alone: the system must abstract hardware and operations for agents while keeping governance legible to people. For Gelsinger, that reconstruction of familiar infrastructure ideas is part of a broader hardware “renaissance.”