Ep. 040 - ASML Is Building a Hybrid Bonding Tool, and We Have the Patents (AI Supply Chain)

Summary

• ASML’s unannounced hybrid bonder would bring its front-end precision into a market led by Besi and other placement specialists. The case rests on 2025 patent filings, with deployment “several years out.” Dies would stay on conveyor carriers through preparation and measurement; ASML moves “the wafer to the die,” applying metrology and wafer-stage strengths as bond pitches tighten.
• Production yield and supplier integration are the critical execution questions for ASML’s conveyor design. Bonding requires six-axis alignment and particle-free surfaces; a single contaminant can wedge open a wider area. Howie questions how moving measurement heads retain accuracy and how several meters of track stay clean; Sherry calls the requirements “almost a front-end process.”
• The speakers do not expect HBM die-to-wafer hybrid bonding before 2029, if at all. A possible best-case 50% capacity gain within the cited 725-micron thickness limit faces higher processing costs, while customers are requesting fewer layers for given bandwidth and performance. Howie’s HBM verdict is “the ROI isn’t there”; logic offers the stronger efficiency case through shorter, denser connections.
• China’s logic-folding roadmap creates another source of demand for hybrid-bonding tools. Howie cites a Huawei phone and its partitioned design, saying it can reach 2.7 GHz, plus roadmaps targeting fully hybrid-bonded data-center accelerators and even three layers by 2030. The associated yield reduction means “more tools for the same yielded output,” reflecting China’s drive to keep scaling under process constraints.
• The clearest evidence of diverging technology paths is already in chip design. Howie contrasts AMD’s cache stacking with Huawei’s partitioning of components inside a core across layers. Sherry sees domestic localization shifting from state direction toward cooperation between fabs and suppliers; export controls “could accelerate” those efforts, though she offers no policy forecast.
• Larger High-NA masks would restore full reticle area and support higher ASML tool prices. Around 2030, 6-by-12-inch masks are intended to overcome the roughly 400 mm² half-field limit versus 850 mm² today, requiring changes across mask production, pellicles, inspection and handling. Sherry connects higher throughput to ASML’s “value-based pricing”; realizing that benefit requires coordination across the supply chain.

Deep dive

1. ASML’s patents sketch a different hybrid bonder

• Howie traces discovery to a Twitter tip from Lithos Crafty and 2025 patent filings; the unannounced tool is “several years out.” Sherry sees reasons to believe ASML is pursuing both wafer-to-wafer bonding, joining whole wafers, and die-to-wafer bonding, placing individual chips. More filings concern the latter, where mature tools meeting both accuracy and throughput requirements are lacking. Sherry says Besi leads die-to-wafer bonding; wafer-to-wafer bonding has more players, including EVG, ASML and PDN, though international incumbents dominate for now.
• The incumbent approach from Besi and ASMPT uses an arm to pick up chiplets, align them and place them onto a stationary base wafer. Howie stresses that placement applies no force; the subsequent anneal completes the bond.
• ASML’s proposed conveyor, with startup SuperTrak as a potential track supplier, keeps each die on one carrier through measurement and plasma activation until bonding. Stations approach the die; finally, the wafer rises to meet it. Howie’s reversal is “the wafer to the die,” drawing on ASML’s metrology and wafer-stage handling.
• As pitches tighten, more signals must fit per square millimeter between dies. Howie argues ASML’s existing sub-nanometer overlay capability offers an order-of-magnitude precision advantage; the challenge is implementing that capability in this unfamiliar bonding architecture.

2. HBM’s hybrid-bonding economics lag logic

• Howie’s primary use case is logic: splitting functional units across two layers shortens communication paths and accommodates more wires than placing blocks side by side. The payoff is power efficiency and more effective silicon area within a constrained footprint.
• For HBM, the main prize is density within a cited 725-micron thickness limit: hybrid bonding might provide 50% more gigabytes in the best case. Thermal benefits are small, and Howie says there may be some signal-integrity benefit, while costs exceed reflow or thermal compression bonding. Customers are actually requesting fewer layers for given bandwidth and performance: “the ROI isn’t there.”
• Sherry points to their economics work on four-high HBM and the accuracy and throughput challenges. Their call is no die-to-wafer HBM hybrid bonding before 2029, if at all. Howie’s rule: “if you don’t have to use hybrid bonding, then you shouldn’t.”
• Jordan challenges that timing with ASML’s 2024 roadmap showing hybrid bonding across NAND and DRAM. Howie cautions that ASML has an incentive to make optimistic forecasts because it wants to sell more tools. He recalls High-NA density projections of 300, 400 and 500 million transistors/mm² that he says remain nowhere near reality: take those forecasts “with a pinch of salt.”

3. Yield depends on six-axis alignment and a spotless track

• Howie separates overlay from cleanliness. Metrology must identify the die’s position on its carrier and the wafer’s position, then compensate in six degrees of freedom, including X/Y displacement, rotation and tilt, before bringing the surfaces together vertically.
• The bond starts with dielectric oxide contact; heating later expands copper into the remaining gap. A particle can lift the surrounding silicon, “forming a wedge,” spoiling an entire area rather than one connection. A clean die must remain clean between every station, Howie emphasizes.
• Sherry says the yield requirements make hybrid bonding “almost a front-end process.” Howie’s open questions are maintaining accuracy as measurement heads move, controlling contamination across a track covering several square meters, and integrating nonstandard stations. ASML may need co-design agreements with preparation-tool suppliers. Howie says ASML could handle the metrology itself, but asks how it will maintain measurement accuracy as the tools move.

4. China’s logic folding raises demand and changes chip design

• Howie’s Huawei example is a C2 handset with a “9050” chip, which he calls the first mobile phone to use hybrid bonding. Moving SRAM to the bottom die lets speed-critical units sit closer together, reducing delays and congestion; he says the design gets up to 2.7 GHz without increasing voltage or power. More silicon running at lower voltage is the basic efficiency argument, with folding adding dense vertical connections.
• Chinese roadmaps target full “logic folding” for data-center accelerators by 2030, at finer bond pitches than TSMC’s SoIC, and even three layers by 2030. Lower yield means “more tools for the same yielded output,” Howie says. Sherry also names NAURA and AMEC as expanding capabilities through acquisitions or investment.
• Jordan asks whether geopolitics will produce separate fab-tool stacks. Howie says divergence is already happening in EDA: AMD’s SoIC partitioning separates cores and L3 SRAM, whereas Huawei and design partners split multipliers, timing relays and buffers within a core across layers. He limits his answer to design.
• Sherry says “we’re not an expert on predicting what the policies could be.” Her observation is that domestic self-sufficiency is shifting “starting from this year” from state-led initiatives toward coordination among fabs, equipment makers and EDA suppliers. She believes that effort will not be affected by policies such as export controls, which could also accelerate it by increasing localization incentives.

5. Larger High-NA masks restore area and support pricing

• Jordan raises ASML’s work with TSMC, IFS and Samsung on larger High-NA photomasks. Howie explains that 8× reduction in one axis and 4× in the other halves the reticle field, limiting die area to around 400 mm² versus 850 mm² today. Interim designs reserve stitching regions or use non-High-NA layers to connect across the boundary.
• Around 2030, a 6-by-12-inch mask would restore the full reticle field and improve throughput. Howie says its long dimension is actually approximately 11.2 inches, “or something like that,” so it fits existing FOUPs and overhead handling equipment. The larger format frees designers from the half-field constraint.
• The change reaches mask production, carriers, pellicles, e-beam inspection and repair. Howie compares the coordination needed to the move from 8-inch to 12-inch wafers in the early 2000s. Sherry connects throughput gains to ASML’s “value-based pricing”: management says higher productivity supports higher tool prices, making the ecosystem transition relevant to long-term revenue per machine.