Summary

SMIC’s N+3 is a meaningful DUV-constrained density step, not wholesale parity with EUV-enabled leading edge. Afzal traces the progression from 2021’s N+1—roughly an 8 nm node without SRAM—to N+2 two years later and now N+3, where M0 shrank by more than 15% and SRAM could be 10–20% smaller. Andrew’s framing: “When one hand is tied behind your back, you figure out a way to innovate,” albeit with visible yield and performance compromises.
Physical teardown uncovered a Kirin 9030 NPU change that benchmarks and Huawei’s disclosures had missed. Kirin 9020 used one “Lite Core” and one Tiny Core; 9030 retains the Lite Core but adds a second Tiny Core. “Nobody knew how to benchmark an NPU,” Afzal says, and Huawei had not described its NPU, making the die map the new evidence.
Huawei’s design response matters as much as SMIC’s process progress. Before restrictions, Huawei was developing on TSMC N5 at about the same time as Apple; moving to SMIC nodes that Afzal calls “much worse, to be honest” forced greater architectural and transistor efficiency. His striking claim is that Kirin 9020 and 9030 improve upon the older Kirin 9000 despite that chip using TSMC N5.
STEEL’s moat is the expensive evidence chain between acquiring a chip and producing an interpretable floor plan. Teardowns consume multiple samples and combine X-ray, mechanical polishing, chemical processing, focused ion beam milling, SEM, and TEM; the last requires specimens only “hundreds of atoms thick.” Andrew argues a credible teardown lab needs “the exact same tools” used to develop advanced technology.
Process-node labels conceal the electrical and library choices that determine usable performance. Smaller cell height and gate pitch increase transistor density but also raise resistance, capacitance, and parasitics; libraries then trade density for drive current, from two-fin high-density cells through three-fin high-performance cells to the four-fin HPC library Afzal says NVIDIA used for A100. Shrinking dimensions is therefore only the opening move.
Backside power, gate-all-around transistors, and sub-micron packaging widen the analytical barrier alongside the manufacturing barrier. Familiar top-down delayering can leave new structures unsupported so “everything just kind of falls apart,” while optical imaging, X-ray, SEM, and TEM leave a costly “no man’s land of technology and capability” between scale and field of view.
Huawei’s “logic folding” is the clearest forward-looking test of whether packaging can substitute for further DUV scaling. The announced approach stacks two chips with roughly 1.5-micron hybrid bonds, versus the stated 6-micron hybrid bonds in AMD V-Cache and MI300, so the layers can “act like a single big circuit.” Afzal stresses that efficiency is still Huawei’s claim, but the strategy could avoid the yield and cost pain of shrinking beyond N+3.

Deep dive

1. STEEL turns destroyed silicon into competitive intelligence

Andrew’s definition is deliberately literal: STEEL takes a device “from the box we get it in all the way down to the transistor,” reconstructing its materials, process integration, electrical design, architecture, and layout. The objective is to show how competitors make decisions within the “same boundary conditions.”
Afzal divides the use cases in two. Competitors can measure how NVIDIA, for example, allocates die area among compute, cache, memory, and I/O; designers can inspect a foundry process before committing their own chip and say, “This is our goal for when we actually make our own chips.”
Sourcing sets the economics. Consumer devices are accessible, but each teardown can consume a “quite ridiculous” number of samples; expensive data-center parts demand careful planning and prior expectations informed by foundry and design disclosures rather than destructive improvisation.

2. Kirin 9030 reveals progress that specifications did not

Afzal’s process chronology starts with SMIC N+1 in 2021, roughly equivalent to an 8 nm node but lacking SRAM and therefore unsuitable for large smartphone chips or AI accelerators. N+2 arrived two years later; N+3 further shrinks M0 by more than 15%, while upper layers move less and SRAM could be 10–20% smaller.
The Kirin floor plan’s novel finding was not its relatively understood CPU or GPU but its NPU. Kirin 9020 contained one Lite Core and one Tiny Core; 9030 shows one Lite Core and two Tiny Cores—an architectural change that benchmarks had not exposed, while Huawei had not described its NPU. Afzal says nobody knew how to benchmark an NPU.
Dylan’s question—worth keeping—was whether publishing that finding created genuinely unique knowledge. Afzal conceded that it was “not super private” because sufficiently capable buyers, including people in China, could purchase chips and create their own die maps; STEEL’s contribution is making the evidence public and interpretable.
Andrew reads SMIC N+3 as a study in forced adaptation: without EUV, SMIC pursued aggressive DUV scaling, echoing Intel’s 10 nm challenges. M0 and several related layers look very clean, but tapered metal profiles, the final etch stop, and seed-layer choices reveal concessions to yield and performance. “They found a way,” and the chips are commercially sold.

3. Density gains survive only if libraries tame their penalties

Afzal reduces transistor scaling to two primary dimensions: cell height and gate pitch. Together they form a “rectangle shape, a grid shape” containing at most one PMOS and one NMOS transistor before design-technology co-optimization, or DTCO, techniques add further density.
Shrinking metal is not free: resistance rises as the conductor narrows and its liner occupies a larger relative share, while capacitance and other parasitics suppress performance. Leading fabs compensate well enough that AMD exceeds 5 GHz on TSMC 5 nm and Intel 7 approaches 6 GHz, the examples Afzal uses to show why nominal size alone is incomplete.
Standard-cell libraries expose the designer’s trade. On N7 and N6, Apple and AMD largely used two-fin high-density libraries; some Qualcomm prime CPU cores used three-fin high-performance cells; NVIDIA’s A100 used a specialized four-fin HPC library, carrying substantially more current.
Export restrictions made that trade unusually consequential for Huawei. Afzal says the company had been developing TSMC N5 alongside Apple, then had to move onto SMIC processes that were “much worse, to be honest.” Its response was to extract more value from every transistor through architecture; he did not emphasize DTCO because N+2 and N+3 appeared broadly unchanged on that dimension.

4. A die map is the end of a destructive evidence chain

Extracting the silicon begins with infrared heating, desoldering, and mechanical separation of a phone’s stacked package, including DRAM, interposer, BGA bumps, and the SoC. Even then, upper routing and power metals conceal the functional floor plan buried near the transistor level.
The lab chemically and mechanically removes those layers down to what is still called “poly,” although Andrew notes that the historic polysilicon name is now a misnomer. High-resolution optical imaging can then distinguish SRAM, logic, and functional blocks—but a sample exposed for a shiny die map can no longer supply every desired cross-section.
A focused ion beam uses gallium ions to mill precise sites selected from that floor plan; SEM covers nanometer-to-millimeter imaging, while TEM resolves fins, gate materials, contacts, and interconnects. TEM’s price is extreme preparation: electrons must pass through a specimen only “hundreds of atoms thick.”

5. Advanced packaging creates the next analytical bottleneck

Andrew argues packaging is advancing “much faster relatively than the transistor technology,” pushing hybrid bonds and interconnects below a micron. Optical tools generally stop around that scale, X-ray struggles beneath it, and electron microscopy offers atomic resolution only across tiny, laboriously prepared regions—the resulting gap is a “no man’s land of technology and capability.”
Backside power changes teardown geometry as well as chip routing. Conventional delayering approaches from the top and land on transistors anchored to bulk silicon; with power routed from the reverse side and gate-all-around channels suspended within different materials, “everything just kind of falls apart” unless the lab develops new preparation processes.
Andrew points to 18A as an example: backside power and gate-all-around already make high-quality floor plans and die maps harder, while failure analysis, fault isolation, and debugging must evolve alongside manufacturing. The analytical constraint therefore affects both independent teardowns and failure-analysis work.
Afzal’s forward-looking client-side example is Huawei’s logic-folding design, which stacks two dies with roughly 1.5-micron hybrid bonds and treats them as one circuit; he compares that with stated 6-micron hybrid bonds for AMD V-Cache and MI300. “That’s what they’re claiming at least”—if the device arrives later this year, a teardown could test whether packaging can help avoid further DUV scaling, which Afzal says could hurt yields and cost more.

Preview: OpenAI's Next Moves and Apple's Trade Secrets Lawsuit 🔬 RL with Verifiable Rewards, but the Verifier is a Lab — Lila Sciences